The frequency spectrum of a digital radio system is broken into channels that are small sub-spectrums. A first transmitter and receiver pair establishes a communication link over a first predetermined channel while other transmitter and receiver pairs use other predetermined channels. The transmitter transmits to the receiver over the channel using a predetermined data rate and modulation scheme, such as binary phase shift keying (BPSK), quadrature phase shift keying (QPSK), binary frequency shift keying (BFSK), or quadrature frequency shift keying (QFSK).
Typically, a data transmission consists of three parts. The first part is an unmodulated carrier signal. The second part is a preamble of known information that is relatively easy for the receiver to detect and to synchronize with. The preamble may be, for example, a period of carrier signal modulated by a known training sequence (e.g., square wave) using a simple modulation scheme (i.e., BPSK). The third part of the data transmission is the modulated waveform that contains the unknown information data bits that are being transmitted.
The data rate of the transmission is usually measured in bits per second (bps), including kilobits per second (Kbps) and megabits per second (Mbps). The number of bits per second is related to the type of signaling (also known as encoding and modulation) that is used to convey the information and the number of times per second that the transmitted signal changes its value. For example, in a phase shift keyed (PSK) digital signal radio system, data is encoded by generating phase shift deviations away from the carrier signal. Decoding the transmitted information entails measuring the phase shift deviations away from the carrier signal and inferring the transmitted information. In a frequency shift keyed (FSK) digital signal radio system, data is encoded by generating frequency shift deviations away from the frequency of a carrier signal. Decoding the transmitted information entails measuring the frequency shift deviations away from the carrier signal frequency and inferring the transmitted information.
A frequency discriminator is a well-known circuit that is used in various applications where the information is coded in the frequency change of a signal (e.g., FSK or PSK). FIG. 2 illustrates conventional frequency discriminator 200 according to an exemplary embodiment of the prior art. Frequency discriminator 200 comprises an in-phase (I) processing path and a quadrature (Q) processing path. The in-phase processing path comprises peak-to-peak limiter 205A, delay line 210A, and multiplier 215A, which may be for example, an exclusive-OR (X-OR) gate. The quadrature processing path comprises peak-to-peak limiter 205B, delay line 210B, and multiplier 215B, which may be for example, an exclusive-OR (X-OR) gate. Frequency discriminator 200 further comprises summer 220, low-pass filter (LPF) 225, and analog-to-digital converter (ADC) 230. Summer 220, LPF 225, and ADC 230 are not required for operation of the invention, but are part of one advantageous embodiment of the present invention.
In the in-phase processing path, peak-to-peak limiter 205A is an amplitude limiter used to remove any parasitic amplitude modulation information on the I input signal to frequency discriminator 200. The output of peak-to-peak limiter 205A is essentially a series of pulses (e.g., a square wave) where the pulse width varies according to the amount of phase shift (i.e., frequency change) between pulses. Multiplier 215A mixes the output of peak-to-peak limiter 205A with a delayed version of itself generated by delay line 210A, thereby creating a DC voltage component at its output proportional to the frequency deviation (phase deviation) in the input I signal.
The quadrature processing path operates similarly to the in-phase processing path. Peak-to-peak limiter 205B is an amplitude limiter used to remove any parasitic amplitude modulation information on the Q input signal to frequency discriminator 200. The output of peak-to-peak limiter 205B is essentially a series of pulses (e.g., a square wave) where the pulse width varies according to the amount of phase shift between pulses. Multiplier 215B mixes the output of peak-to-peak limiter 205B with a delayed version of itself generated by delay line 210B, thereby creating a voltage component at its output proportional to the frequency deviation (phase deviation) in the input Q signal.
The outputs of the in-phase processing path quadrature processing path are then added by summer 220. The output of summer 220 is nominally a series of positive and negative pulses having varying duty-cycles. LPF 225 operates as an integrator that recovers the DC component of the output of summer 220. The output of LPF 225 is then converted to digital samples by ADC 230.
The conventional way of delaying the signal is to use a tank circuit. FIG. 3 illustrates conventional delay line 210 using a tank circuit made of discrete components according to an exemplary embodiment of the prior art. Delay line 210 comprises two capacitors, C1 and C2, and an inductor, L1. However, in this scheme, there are a number of problems, including:                1) When the signal frequency is low, the component values become large and are therefore difficult to integrate on a single integrated circuit chip. Using external discrete components requires that two extra chip pins (IN and OUT) be added; and        2) Tracking process variations, as well as supply voltage fluctuations and temperature, is difficult and inaccurate.        
Another common prior art method performs the discriminator function in the digital domain. A digital discriminator has the advantage of extremely accurate timing (e.g., the delay is N times the clock period), but suffers from time quantization problems, which lead to phase quantization problems. As a result, the minimum detectable phase shift is equal to one clock cycle of the sampling clock. This typically leads to an extremely high clock rate, higher power, and the requirement of generating a clock at a much higher frequency than is typically required for the rest of the chip.
Therefore, there is a need in the art for improved frequency shift keyed (FSK) receivers and phase shift keyed (PSK) receivers that are capable of more accurately detecting frequency (or phase shifts) in the incoming signal. In particular, there is a need for an improved frequency discriminator for use in FSK and PSK receivers. More particularly, there is a need for an improved frequency discriminator that does not rely on delay lines made from discrete components.